1. Field of the Invention
The present invention relates generally to analog-to-digital converters (ADCs) and in particular, to high speed algorithmic ADCs having over-range correction.
2. Description of the Related Art
Algorithmic ADCs are categorized as either pipelined or cyclic. Pipelined ADCs are commonly used in low- power, high speed applications. A typical pipelined architecture uses a number of similar stages connected in series. A cyclic ADC is typically includes two similar stages, with the final stage output connected back to the initial stage input.
Referring to the drawings, FIG. 1 depicts a single stage 20 of a conventional pipelined ADC. Each stage produces K number of bits (D.sub.1 -D.sub.k) so that an ADC having J number of stages will produce J*K number of bits N. FIG. 2 depicts an ADC having a multiple stages, including three stages 20A, 20B and 20C, with each stage producing a single bit D.sub.1 -D.sub.3, respectively.
Each converter stage 20 (FIG. 1) includes a sample and hold circuit (S/H) 22 which receives the analog input Vres.sub.i-1 and produces an output Vres.sub.i. The output Vres.sub.i, sometimes referred to as the residue voltage, is fed to the following stage which produces a residue voltage Vres.sub.i+1. For the input stage 20A (FIG. 2), the input voltage Vin is represented by Vres.sub.i-1 and the output voltage is represented by Vres.sub.i.
The output of the sample and hold circuit 22 is fed to a an analog-to-digital subconverter circuit (ADSC) 26A having a K bit output. Typically, the ADSC circuit 26A is implemented using comparator circuits which compares Vres.sub.i-1 to a reference voltage Vref. By way of example, stage 20A (FIG. 1) produces a single bit (K=1) and utilizes a single comparator which compares Vres.sub.i-1 (Vin) with a reference voltage and provides an output D.sub.1 which is either +1 or -1 depending on the magnitude of Vres.sub.i-1. Typically, Vres.sub.i-1 can vary between -Vref and +Vref so that the reference used by the comparator is the mid-point between the reference voltages which is nominally 0 volts.
The digital output of the ADSC 26A is converted to an analog voltage by a DAC 28A having K input bits. The output voltage of DAC 28A is subtracted from voltage Vres.sub.i-1 held by the sample and hold circuit 22 by adder 24. The difference output of adder 24 is multiplied by an amplifier stage 30A having a gain of 2.sup.K. The amplifier output Vres.sub.i is forwarded to a subsequent stage 20 which provides additional analog and digital outputs based upon the magnitude of Vres.sub.i. As will be explained later in greater detail, each stage typically alternates between two modes of operation, including a sample phase followed by an amplification phase. When a stage 20A (FIG. 2) is in an amplification phase, the subsequent stage 20B will be in the sample phase. The magnitude of the residue voltage Vres.sub.i at the end of the amplification phase can be calculated by the following equation, where Vdac.sub.i is the output of DAC 28A: EQU Vres.sub.i =2.sup.K (Vres.sub.i-1 -Vdac.sub.i) (1)
As previously noted, a cyclic ADC includes two stages similar to that of FIG. 1, each of which alternates between a sample and an amplification phase. The input voltage is applied to the first stage which produces a first residue voltage and a first digital output. The first stage forwards the residue voltage to the second stage, with the second stage generating a second residue voltage and a second digital output. The second residue voltage is fed back to the input of the first stage where the first stage produces a third residue voltage and third digital output. The residue voltage is recirculated in this manner until the desired number of bits are produced.
The central problem with any algorithmic ADC is that the overall linearity of the ADC is determined by the linearity of DAC 28A. An attractive solution, especially for high speed applications, is to use a one bit (K=1) ADSC 26A and DAC 28A. With a single bit decision, there is always a straight line that can be drawn between the positive and negative references. As indicated by equation (1), when K=1, the ideal gain of the converter stage is two. This is demonstrated by the following equation derived from equation (1): EQU Vres.sub.i =2.multidot.Vres.sub.i-1 -D.sub.i .multidot.Vref(2)
Value D.sub.i is either .+-.1 and Vres.sub.i-1 has a minimum value of -Vref and a maximum value of +Vref. FIG. 3 depicts an ideal one bit per stage residue transfer function. The transfer function includes a single transition at Vref=0 and a nominal gain of 2.
FIG. 4 is a conventional circuit typically used to provide the one bit per stage residue transfer function of FIG. 3. The stage is shown as a single ended stage in order to simplify the description of operation. However, as is well known, such stages are usually actually implemented in fully differential form where there are differential input residue voltages and differential output residue voltages.
The single ended FIG. 4 stage includes a pair of capacitors C1 and C2, which are nominally of the same value, and an operational amplifier 32. Switches S1A, S1B, S1C, S2A and S2B are provided which are implemented using transistors and are controlled by two non-overlapping clocks.
During the sample phase, one of the clocks causes switches S1A, S1B and S1C to be turned on, with switches S2A and S2B remaining off. The equivalent circuit is shown in FIG. 5A. Amplifier 32 is configured as a voltage follower (unity gain), with the input voltage Vres.sub.i- 1 being applied to one side of both capacitors C1 and C2. Since the inverting input of amplifier 32 is nominally at ground potential due to feedback, the entire input voltage Vres.sub.i-1 is applied across the parallel combination of capacitors C1 and C2.
During the amplification phase following the sampling phase, switches S1A, S1B and S1C are turned off and switches S2A and S2B are turned on. The equivalent circuit is shown in FIG. 5B. Capacitor C2 is connected between the inverting input and the output of amplifier 32 and one side of capacitor C1 is connected to either +Vref or -Vref depending upon bit D.sub.i. As can be explained by the principle of conservation of charge, at the termination of the amplification phase, the output voltage Vres.sub.i will nominally be equal to twice input Vresi.sub.1 plus Vref when D.sub.i =+1 and twice input Vres.sub.i-1 minus Vref when D.sub.i =-1. Thus, the nominal transfer characteristics shown in FIG. 3 are achieved.
Taking into account various sources of error, the output voltage Vres.sub.i is more accurately determined by the following equation: EQU Vres.sub.i =((2+a.alpha..sub.i).multidot.Vres.sub.i-1 -(1+.alpha..sub.i).multidot.D.sub.i .multidot.Vref).multidot.(1-.epsilon..sub.i)+Vofs.sub.i (3)
As can be seen from equation (3), the actual output voltage Vres.sub.i is affected by .alpha..sub.1, the capacitor mismatch between C1 and C2, ei, the error due to finite open loop gain of amplifier 32 and settling, and Vofs.sub.i, representing a total offset term due to the charge injection effects and amplifier 32 input offset.
The converter stage errors noted in connection with equation (3)affect the linearity of the overall ADC. Some of the errors attributable to amplifier 32 can be minimized by careful amplifier design. However, there is a technological limit to reducing the error due to capacitor mismatches. For resolution higher than ten bits, several calibration/correction techniques have been developed to address capacitor mismatch.
The relative accuracy of an ADC is the deviation of the output from a straight line drawn through zero and full scale. Such relative accuracy is sometimes referred to as integral non-linearity error. Differential non-linearity (DNL) error describes the difference between two adjacent analog input signal values compared to the step size. For certain applications such as digital imaging, only the DNL is critical. A commutated feedback capacitor switching technique has been developed to reduce the DNL even for relatively large capacitor mismatches. This technique relies on the observation that the DNL is determined by the height of the transition gap in the transfer characteristic. As shown in the idealized transfer curve of FIG. 3, the height V.sub.D is 2Vref at the transition between D.sub.i =+1 and D.sub.i =-1.
The significance of the height V.sub.D can be best appreciated by considering an input voltage Vres.sub.i-1 having a magnitude very slightly less than transition voltage (0 volts) and an input voltage very slightly greater that the transition voltage. In order to achieve the desired DNL, the output of the ADC should change no more than one LSB for the slight change in input voltage. However, since the difference in capacitor values represented by .alpha..sub.i are random errors which cannot be reduced to an insignificant value in high resolution ADCs, the approach depicted in FIG. 4 cannot be used in such applications.
A prior art commutated feedback-capacitor switching (CFCS) technique has been developed to maintain a high DNL despite the presence of a significant capacitor mismatch. The FIG. 4 circuit is modified to include additional switches so that, during the amplification phase, capacitors C1 and C2 are reversed in the circuit depending upon the state of bit D.sub.i. The equivalent circuit during the sample phase remains the same as shown in FIG. 5A. However, the equivalent circuit during the amplification stage is changed from FIG. 5B to the circuit shown in FIG. 6. When D.sub.i =+1, capacitor C1 is connected as the input capacitor and C2 is connected as the feedback capacitor. When D.sub.i =-1, the two capacitors are switched so that C2 is connected as the input capacitor and Cl functions as the feedback capacitor.
FIG. 7 shows the transfer curve when CFCS is utilized. Neglecting the errors due to amplifier 32 settling time and finite gain, the output voltage in the region D.sub.i =-1 is given by the following equation: ##EQU1##
Similarly, the output voltage when Di=+1 is given by the following equation: ##EQU2##
The magnitude of V.sub.D is calculated by subtracting the value of Vout for Vin=0, in accordance with equation (4), from the value of Vout for Vin=0, in accordance with equation (5). The result V.sub.D (.DELTA.Vout.sub.Vin=0) is as follows: ##EQU3##
It can be seen from equation (5) that V.sub.D (.DELTA.Vout.sub.Vin=0) is equal to 2Vref up to a second order error term.
Another major issue for any algorithmic ADC is the linear range in the analog domain. The description of prior art converters so far has assumed that all of the analog stages have been operating in the linear range. However, the linear range is limited by the circuit characteristics and is, in no case, greater than the power supply voltage. For a converter architecture which has only 1-bit conversion stages, should the analog residue in one stage be outside the -Vref to +Vref range, such analog residue will be amplified by 2 at each subsequent stage and eventually reach a limiting region of the output voltage at a later stage. This situation results in an erroneous ADC output.
One solution is to use one or more over-range stages capable of operating with analog inputs greater than -Vref to +Vref. Examples of the prior art two bits per stage approach are described in "A Pipelined A/D Conversion Technique With Near-Inherent Monoticity" by Paul C. Yu, et al., IEEE Transactions On Circuits and Systems II, Vol. 42, July, 1995, pp. 500-502 and in "A 2.5 V, 12-B, 5-MSample/s Piplelined CMOS ADC" by Paul C. Yu et al., IEEE Journal of Solid State Circuits, Vol. 31, December 1996, pp. 1854-1861. Examples of the over-range circuits are disclosed in U.S. Pat. No. 5,668,549 entitled "Radix 2 Architecture and Calibration Technique For Pipelined Analog To Digital Converters" which issued on Sep. 16, 1997. The contents of the two IEEE publications and U.S. Pat. No. 5,668,549 referenced above are hereby fully incorporated herein.
FIG. 8 depicts an exemplary prior art over-range circuit which produces two bits per stage. FIG. 9 is the residue transfer function of the FIG. 8 circuit. Although not depicted in FIG. 8, three comparator circuits are used to determine the two bit digital code based upon input Vin which further defines the three transition points (-Vref, 0, +Vref) in FIG. 9 transfer function. During the sampling phase, switches S1A, S1B, S1C, S1D and S1E are closed so that amplifier 32 is configured for unity gain and so that voltage +Vref is applied to capacitor C0, -Vref is applied to capacitor C3 and the input Vres.sub.i-1 is applied to both capacitors C1 and C2.
Table 1 below illustrates the operation of the FIG. 8 circuit when the circuit is in the amplification phase.
TABLE 1 ______________________________________ Digital Region Code C0 C1 C2 C3 ______________________________________ Vin &lt; -Vref -1 S2A S4B S4C S1D -Vref &lt; Vin &lt; 0 S1A S2B S4C S1D 0 &lt; Vin &lt; +1 S1A S3B S2C S1D +Vref +Vref &lt; Vin +2 S1A S3B S3C S2D ______________________________________
By way of example, when Vin is between -Vref and 0, Table 1 indicates that the comparators (not depicted) will generate digital code 0. As also indicated by Table 1, switch S1A (FIG. 8) will be turned on thereby connecting associated capacitor C0 to +Vref. Switch 2B will be turned on so as to connect capacitor C1 across amplifier 32 thereby providing feedback. Switches S4C and S1D are also turned on thereby connecting both capacitors C2 and C3 to -Vref. The result is that Vref/2 is added to the input voltage Vres.sub.i-1 and the sum is multiplied by two to provide the transfer characteristics illustrated in FIG. 9. Operation when the digital code Di=+1 is similar, except that Vref/2 is subtracted from the input voltage Vres.sub.i-1 and the difference is multiplied by two.
In the event an over-range condition exists where input voltage Vres.sub.i-1 is less than -Vref (D.sub.i =-1), -Vref is connected to capacitors C1, C2 and C3, with CO being connected as the feedback capacitor. This causes 3/2Vref to be added to the negative input voltage Vres.sub.i-1 and the sum to be multiplied by two. This causes the residue voltage to become positioned in-range thereby preventing over-ranging from occurring in subsequent stages. Further, the digital output code of -1 indicates that over-range correction has occurred thereby enabling well known over-range correction techniques to be used so that the output code of the ADC will be correct. Exemplary correction techniques are disclosed in previously cited U.S. Pat. No. 5,668,549.
In the event that input voltage Vres.sub.1-i is greater than Vref, digital code +2 is generated thereby indicating an over-range condition. As indicated by Table 1, switches S1A, S3B and S3C connect +Vref to capacitors C0, C1 and C2, respectively. Switch S2D connects capacitor C3 to the feedback position. This causes 3/2Vref to be subtracted from the input voltage Vres.sub.i-1 and the difference to be multiplied by two so that the residue voltage will be in range. The digital code +2 is used for over-range correction. Note that for each of the four different digital codes, a different one of the four capacitors is placed in the feedback position thereby providing commutated feedback capacitor switching (CFCS) so as to compensate for capacitor mismatching and thereby achieving a low DNL error.
The major drawback to the FIG. 8 over-range stage is reduced operating speed due to the low feedback gain (C/4C or .beta.=1/4) compared with the normal conversion stage of .beta.=1/2 (C/2C) of FIG. 4. Feedback gain is defined herein to mean that fraction of the amplifier output that is feed back to the input. For the same settling of the over-range stage, the amplifier 32 bandwidth requirements are also increased over the normal stage.
The present invention overcomes the above-described shortcomings of the prior art. An ADC stage is disclosed that provides both over-range correction and compensation for capacitor mismatching so as to provide a low DNL error and yet is capable of operating at significantly greater speeds than such prior art stages. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.